The present invention relates to a semi-conductor integrated circuit, and more particularly to a circuit for a high speed, low power consumption Table Look aside Buffer using a content addressable memory mounted on a microprocessor LSI.
A cache memory is provided between a central processing unit and a main memory of a computer system in order to speed up the operation speed, the cache memory functioning as a high speed buffer memory and storing a portion of programs and data to be stored in the main memory.
Virtual addresses are used with recent central processing units so that address translation is required between virtual addresses and real addresses of the cache memory and main memory. Since the size of a translation table becomes large as the address space becomes large, the table is generally structured hierarchically. It takes some time to refer to the hierarchical table and find a real address. In order to obtain a real address at high speed, tables having an associative function called a Table Look aside Buffer (TLB) are provided in parallel as hierarchical tables.
TLB is therefore required to execute address translation at high speed and also at high hit probability while using a small circuit scale.
Two types of associative schemes, full associative and set associative, are used for TLB. With the former scheme, an input address is compared with all data stored in TLB to check coincidence/non-coincidence therebetween. If there is coincident data stored in TLB, a signal indicating a data presence and the stored data are output.
With the latter set associative scheme, candidates of coincident data are selected, and an input data is compared with these candidate addresses to check coincidence/non-coincidence therebetween. If there is coincident data, a signal indicating a data presence and a real address corresponding to the coincident data are output.
As above, since the full associative scheme compares all data, the number of comparators increases and the circuit area becomes large. In order to suppress an increase in the circuit area, a simple circuit having a small area is used as the comparator. Therefore, a time required for data comparison becomes long, and because of a number of comparators, power consumption becomes great. Although there are such disadvantages, a data coincidence probability becomes high because the comparison is executed for all stored data.
In the case of TLB of the set associative scheme, the number of comparators is as small as two to four sets because candidates for compared data are selected and the coincidence/non-coincidence check is performed only for these candidates. Accordingly, a high speed comparator circuit can be used and coincidence detection can be performed at high speed, although the comparator circuit becomes complicated. However, a restriction of candidate selection lowers a data coincidence probability. Therefore, a coincidence probability generally equal to the full associative TLB cannot be obtained unless the scale of the TLB storage circuit is increased by about a fourfold. This expansion of the circuit scale increases the number of operating circuits, leaving some issues of an increased power consumption and an increased circuit area.
An example of a coincidence-detecting circuit for the full associative scheme is described in JP-A-59-231789 in which a coincidence-detecting circuit is provided independently for each memory cell for the comparison between search data and stored data. An example of a coincidence-detecting circuit of this type for higher speed operations is described in IEEE Journal of Solid State Circuits Vol. 28, No. 11, pp. 1078-1083. According to this report, a reference signal line is provided in parallel with a coincidence-detecting signal line and also with a current supply line, and a differential type NOR gate is formed by coincidence-detecting MOSFETs, for the purpose of high speed detection. This approach has a restriction of the circuit area because of a need of three wiring lines, although high speed operation is realized.
An example of TLB of the set associative scheme is described in JP-A-60-117495 in which a circuit for the comparison with search data utilizes a sense amplifier for reading memory cell data.
An object of the invention is to provide a high speed, low power consumption data coincidence-detecting circuit and TLB using this circuit, TLB (Table Look aside Buffer) being of the full associative scheme.
The issues of the above-described prior art are high speed, low power consumption, and small circuit area. If the operation speed and consumption power of TLB of the full associative scheme can be made equal to or better than those of TLB of the set associative scheme, TLB with a higher coincidence probability can be obtained by using TLB of smaller scale (integration).
For the first issue of speeding up the data coincidence detection of an associative memory, a reference potential is generated for the comparison with a coincidence signal line potential. High speed operation can be realized through coincidence detection by a differential amplifier circuit by using the reference potential. In the coincidence detection by the differential amplifier circuit in static operation by using the reference potential, a small change in voltage can be detected, and in addition because a margin for timing adjustment is not required, high speed operation can be realized.
For the second issue of low power consumption of a coincidence-detecting circuit, the potentials of a coincidence signal line and a reference signal line are maintained in advance at a MOSFET threshold voltage value or lower and only the potential of the coincidence signal line is raised high to operate the detection circuit. In this manner, the potentials of the non-coincidence signal line and the reference signal line allow current to hardly flow through MOSFETs and the differential detection circuit is operated only during the period necessary for signal detection. One to four sets of high speed comparator circuit are additionally provided for an input address. The coincident addresses of past data up to one to four sets are output from the memory circuits storing the corresponding data sets, without operating the main unit of TLB. In this manner, high speed and low power consumption are realized. A coincidence of three to five bits of the input address is checked by a pre-comparator, and power is supplied only to comparators corresponding to the coincident addresses. In this manner, the number of operations of comparators can be reduced to xe2x85x9 or more, and the power consumption can be reduced to ⅕ or more.
The circuit of this invention uses a differential amplifier circuit for a coincidence detection of an associative memory. A coincidence-detecting circuit is operating in a pulsate manner, and one to four sets of pre-comparator circuits are provided. In accordance with a comparison result by the pre-comparator circuit, only the coincidence-detecting circuits corresponding to the coincident addresses are supplied with power. In this manner, power can be supplied in a concentrated way both in the time and space so that low power consumption can be realized without degrading high speed operation.
In the circuit of this invention, a predetermined current is supplied to the coincidence-detecting signal line of the associative memory, and a change in the potential of the coincidence-detecting signal line is checked to detect a coincidence/non-coincidence to thereby speed up the operation of the detector circuit and simplify the circuit. In order to check a potential change of the coincidence-detecting signal line at higher speed, the reference signal line is provided and a potential difference between both the lines is detected by a differential amplifier circuit, to achieve a faster operation. The coincidence-detecting circuit is operated in a pulsate way, and one to four sets of pre-comparator 25 circuits are provided. In accordance with a comparison result, only the coincidence-detecting circuits corresponding to the coincident addresses are supplied with power. Therefore, it is possible to supply power in a concentrated manner both in the time and space and the low power consumption can be realized without degrading the high speed operation.